Each memory cell in a dynamic random access memory (DRAM) is constructed from a single transistor and a single capacitor and is called dynamic because its data decays and become invalid due to various leakage current paths to surrounding cells and to the substrate the DRAM resides upon. To keep the data in the cells of any DRAM valid, each memory cell is periodically refreshed. Data in the DRAM cell array is refreshed every time it is read out of the cell array into the sense amplifiers and subsequently rewritten into the cell. The memory controller is responsible for periodically performing refresh maintenance operations on the memory cell array. Every row of the memory array needs to be refreshed before the data in the row decays to an invalid state.
As the densities and the page sizes of DRAM grow, it takes significantly more power and time to perform a refresh on the entire memory cell array. With increasing densities, DRAM devices are internally refreshing more rows per refresh command to keep the refresh interval constant, which results in significant power peaks during a given refresh operation. Furthermore, when DRAM is being refreshed, it can't perform normal read and write operations and is effectively locked out from normal operating mode. Thus, with multiple rows refreshed per refresh command, the lockout period has been increasing. The increasing lockout period increases refresh latencies and, as a result, lowers the bandwidth that can be guaranteed for isochronous traffic.